1. Field of the Invention
This invention relates generally to a method and apparatus for arranging alignment marks for use in a manufacturing process of a semiconductor device, and more particularly, for use in aligning to alignment marks on a wafer of the semiconductor device.
2. Discussion of the Related Art
There are many processes which require alignment to alignment marks on a wafer in the manufacturing of a semiconductor device. For example, in the case of forming a film on the wafer and then forming a given pattern on the thus formed film, a reticle (having an original image of a pattern,) and the wafer are accurately aligned with each other, and thereafter the image or pattern on the reticle is exposed on the film. Such an alignment is performed by aligning an alignment mark on the reticle with an alignment mark on the wafer.
When semiconductor devices are fabricated or put down on a wafer, the semiconductor devices are formed in regions called active areas of the wafer. The active areas of the wafer contain the semiconductor devices being manufactured. After formation, the semiconductor chips are individually cut apart with a cutting device. The cutting device has a finite cutting width. Such a device, in standard practice, includes for example, a diamond saw. To provide an adequate spacing for the cutting width between chips, an area is put in between all of the active areas on the wafer. Such an area is referred to as the kerf. The way in which a wafer is typically designed is that there is some portion of the kerf region remaining on the top, bottom, left and right side edges of the semiconductor chip subsequent to the chip being diced (i.e., when the individual chip has been diced from the wafer).
Typical practice includes designing the kerf so that some portion of the kerf is at the top, bottom, left and right of an active area. Measurement marks and alignment marks are typically placed in the top, bottom, left-hand and right-hand side kerf areas for use by measurement and alignment tools during manufacturing of the semiconductor devices on the wafer. The measurement marks and alignment marks are typically formed on the wafer during a manufacture thereof. The specific type and number of alignment marks depends upon the particular alignment tool being used. For example, there may be as few as two alignment marks, up to a family of marks. As mentioned, the specific type and number varies from alignment tool to alignment tool. For example, SVGL Micrascan is a particular type of alignment tool and Axiom is a particular alignment system.
In the manufacture of semiconductor devices, an alignment system is used in conjunction with a lithography tool. At a first level, a reference pattern is put down on a blank wafer. The alignment tool and lithography tool utilize the reference pattern in connection with patterning of subsequent layers. That is, the alignment system is used to align the lithography tool for the patterning of subsequent layers. The alignment tool makes reference to the alignment marks put down on a previous level, for aligning the lithography tool in conjunction with a present level.
There are a variety of different kinds of designs for individual alignment marks. For example, the alignment marks may include squares arranged in a grating. Similarly, the alignment marks may include a phase grating or series of lines. An alignment tool generally has optics and an encoder, wherein the alignment tool registers to (and locates based upon) what it sees in effect when viewing the alignment marks.
Referring to FIG. 1, such an alignment mark 10 is frequently formed within a kerf 12 on a wafer 14, the kerf 12 being a region between adjacent semiconductor chips 16, 18 on the wafer 14 defining the dicing channel between chips 16, 18. The dicing channel typically has a width on the order of less than the width of the kerf 12.
Alignment marks, as currently designed and known in the art, are limited by an amount of signal (i.e., signal characteristic) required for correctly processing a mark location with a particular alignment system. For example, with a commercially available Micrascan optical alignment system, chevrons (as shown in FIG. 1) can be no less than fifty-five microns (55 .mu.m) in length versus a manufacturer's recommended value of seventy microns (70 .mu.m). According to the Micrascan manufacturer, 70 .mu.m is the point at which the signal level of a detected chevron begins to diminish. Chevrons are alignment marks for use with alignment systems. Chevrons
typically include a pattern having the shape of a V or an inverted V. As such, the kerf must be at least 110 microns in width to accommodate both alignment marks.
In general, alignment marks are the largest structures in the kerf 12. Historically, the alignment mark has not been a limiter to manufacturing productivity because of the width of the dicing channel. The dicing channel width has typically been on the order of 135 micrometers (.mu.m). The width of the dicing channel has also typically been determined as a function of the cutting or dicing tool cutting capability, that is, as dictated by an ability of the cutting tool to cut within a certain thickness channel, which is a combination of dicing saw width plus an allowance for local saw damage. With advancements in semiconductor manufacturing technology, new narrower dicing saws (developed for use with backside thinned semiconductor wafers) allow for much smaller dicing channels having widths on the order of 80 micrometers (.mu.m). As a result, the productivity of the wafer is thus disadvantageously limited by the size of an alignment mark, because in order to fit both alignment marks the kerf width must be at least 110 microns.
In U.S. Pat. No. 5,496,777, entitled "Method of Arranging Alignment Marks," issued to Moriyama on Mar. 5, 1996, alignment marks are placed in contact with a scribing line. The alignment marks of the '777 patent furthermore extend into the active area of a semiconductor chip. The method of arranging alignment marks according to the '777 patent thus undesirably consumes valuable semiconductor real estate and the active area of the semiconductor wafer is not maximized. In addition, the kerf width L1 of the semiconductor wafer shown in the '777 patent is not made any smaller by the use of the alignment marks as taught therein.
It would thus be desirable to make alignment marks that fit within a narrower dicing channel to allow for a significant productivity improvement, without reducing alignment mark size.